Parallel processor implementation of net routing

Details Parallel processor implementation of net routing Parallel processor implementation of net routing

1997-02-11

1999-07-27

Trammell, James P.

39550008, G06F 1750

Patent

active

059305002

ABSTRACT:
A method for maximizing effectiveness of parallel processing, using multiple processors, to connect pins of a net of an integrated circuit is disclosed. The method requires the pins to be partitioned into sets of pins and the sets of pins to be further partitioned into meta-sets of the sets of pins. The sets and the meta-sets are connected using a minimal spanning tree algorithm, and the connected sets are made to share a pin, thereby ensuring that the whole net is interconnected without creating a loop in the routing. In addition, because the partitions and the sets of partitions average approximately the same number of pins, the work load can easily be balanced between the processors.

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Mayrhofer et al., "Congestion-Driven Placement Using a New Multi-Partitioning Heuristic," 1990 IEEE, pp. 332-335, 1990.
Tragoudas, "Min-Cut Partitioning on Underlying Tree and Graph Structures," 1996 IEEE, pp. 470-474, 1996.

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