Memory system using a flash memory and method of controlling the

Static information storage and retrieval – Addressing – Plural blocks or banks

Patent

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36523004, G11C 800

Patent

active

059301937

ABSTRACT:
A memory system includes a flash memory having a plurality of individually erasable physical blocks, table section for holding the relationship in correspondence between the logical blocks allocated by the allocation section and the physical blocks first counting and managing section for counting and managing write counts of the respective logical blocks, first classifying section for classifying the logical blocks into a plurality of groups on the basis of the respective write counts of the logical blocks, erasure section for erasing data in a physical block allocated to a logical block to produce a free physical block, second counting and managing section for counting and managing the erasure counts of the respective physical blocks, second classifying section for classifying the physical blocks into a plurality of groups on the basis of the respective erasure counts of the physical blocks, control section for allocating the respective logical blocks to the physical blocks; and managing section for managing free physical blocks which are not allocated to any logical blocks.

REFERENCES:
patent: 5408628 (1995-04-01), Ameti
patent: 5434825 (1995-07-01), Harari
patent: 5633824 (1997-05-01), Onuki
patent: 5671439 (1997-09-01), Klein et al.
patent: 5737742 (1998-04-01), Achiwa et al.

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