Flash memory with adjustable write operation timing

Details Flash memory with adjustable write operation timing Flash memory with adjustable write operation timing

1998-03-20

1999-07-27

Nelms, David

Static information storage and retrieval

Floating gate

Multiple values

36518522, 36518533, 365226, G11C 1604

Patent

active

059301686

ABSTRACT:
A flash memory is described which includes circuitry to determine how many memory cells can be programmed in a single write operation by measuring the power available for programming. The available power is determined by monitoring Vcc and/or Vpp prior to performing a data write operation. The memory control circuit adjusts the memory write operation based upon the actual operating conditions and is not limited in performance to anticipated specification limits. A method is described which reduces the number of total write operations by performing a limited number rewrites in place of individual rewrite operations by rewriting only memory cells which where not properly programmed. Rewrite operations of properly programmed memory cells is avoided to reduce the total number of write operations.

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