Taper isolated ram cell without gate oxide

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357 22, H01L 2702, H01L 2980

Patent

active

043285112

ABSTRACT:
The present invention is embodied in a dynamic random access memory (RAM) cell comprising a depletion mode field effect transistor structure with a p-n junction "gate" electrode. The cell can be programmed to two threshold voltage states providing constant current sensing. Cell programming is by application of appropriate signals to the transistor "gate" electrode and source. Reading is accomplished by sensing current through the transistor while the source is grounded. An intermediate voltage on the "gate" electrode prevents changes in the state of the cell.

REFERENCES:
patent: 3868718 (1975-02-01), Arai
patent: 4126899 (1978-11-01), Lohstroh et al.
Arai "Charge-Storage Junction Field-Effect Transistor", IEEE Trans. Electron Devices, vol. ED-22 (4/75), pp. 181-185.
Heald et al., "Multilevel Random-Access Memory using one Transistor per Cell", IEEE J. Solid-State Circuits, vol. SC-11 (8/76), pp. 519-528.

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