Error correcting system for correcting two or three simultaneous

Details Error correcting system for correcting two or three simultaneous Error correcting system for correcting two or three simultaneous

1982-02-16

1984-08-28

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

044687699

ABSTRACT:
An improved two or three error correcting system for BCH code (Bose, Chaudhuri, Hocquenghem code) has been found. In case of a two error correction system, a first syndrome A.sub.1 and a second syndrome A.sub.2 are obtained from a reception code C'=(a.sub.1 ', a.sub.2 ', . . . , a.sub.n '): ##EQU1## Then, S.sub.1 =A.sub.1 +.alpha..sup.n-t, and S.sub.2 =A.sub.2 +.alpha..sup.3(n-t) are obtained, for every value of t, where n is a code length, t is an integer equal to or less than n, and .alpha. is a primitive element of a Galois field. When A.sub.1 .noteq.0, a t'th bit a.sub.t ' is corrected by inverting the same on the condition that the t'th bit of S.sub.2 is equal to the t'th bit of S.sub.1.sup.3. When A.sub.1 =0, it is clear that no error exists, and no correction is performed. In case of a three error correction system, a third syndrome ##EQU2## and S.sub.3 =A.sub.3 +.alpha..sup.5(n-t) are obtained further for every value of t, and a correction is performed by inverting the t'th bit according to the value of EL(t)=S.sub.1.sup.6 +S.sub.2.sup.2 +S.sub.1.sup.3 S.sub.2 +S.sub.1 S.sub.3 when A.sub.1.sup.3 +A.sub.2 .noteq.0, or the value of S.sub.1 when A.sub.1.sup.3 +A.sub.2 =0. The structure of the present system is simple since said values S.sub.2, S.sub.3 and EL(t) are obtained merely by a ROM table and an exclusive-OR circuit.

REFERENCES:
patent: 3781791 (1973-12-01), Sullivan
patent: 4030067 (1977-06-01), Howell et al.
patent: 4064483 (1977-12-01), Takezono et al.
patent: 4099160 (1978-07-01), Flagg
patent: 4107652 (1978-08-01), Tanahashi et al.
patent: 4360916 (1982-11-01), Kustedjo et al.

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