Jitter tolerant circuit for dual rail data

Details Jitter tolerant circuit for dual rail data Jitter tolerant circuit for dual rail data

1988-05-31

1989-11-07

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

307265, 328 58, 375118, H03K 505, H04L 700

Patent

active

048797308

ABSTRACT:
A retiming circuit is provided which accurately converts half-width dual rail data with up to one unit interval of jitter with respect to the data clock, into full-width data. The circuit is comprised of D-flip-flops and associated logic elements which capture and hold a data pulse until the captured data pulse can be accurately transferred to the next circuit stage by a positive clock transition.

REFERENCES:
patent: 4017803 (1977-04-01), Baker
patent: 4218770 (1980-08-01), Weller
patent: 4694340 (1987-09-01), Tanaka
patent: 4726045 (1988-02-01), Caspell et al.

Affiliated with

Also associated with

Rating

Jitter tolerant circuit for dual rail data does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Jitter tolerant circuit for dual rail data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Jitter tolerant circuit for dual rail data will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-87718