Microprocessor having self-programmed eprom

Details Microprocessor having self-programmed eprom Microprocessor having self-programmed eprom

1986-09-25

1988-12-27

Eng, David Y.

Boots, shoes, and leggings

G06F 922

Patent

active

047945583

ABSTRACT:
A single-chip microcomputer comprises a CPU (1), a RAM (2), an EPROM (3), a timer (4), serial I/O communication logic (5), four I/O ports (11-14) and an input pin for providing a RESET signal or programming potential V.sub.PP (23). An EPROM control register (53) in the CPU is loadable under the control of a computer program stored in an external memory (40). Responsive to a first bit in the EPROM control register an address buffer/latch 61 and a data latch 62 temporarily latch address and data information during a write operation to the EPROM. Responsive to a second bit in the EPROM control register the programming potential is applied to the EPROM for a predetermined time to program the data information into the EPROM at its associated address. The accuracy of the programming operation may be verified using the CPU under the control of the external computer program, to compare the address and data information programmed into the EPROM with the original source of such information.

REFERENCES:
patent: 3978457 (1976-08-01), Check et al.
patent: 4018565 (1977-04-01), Fletcher et al.
patent: 4045660 (1977-08-01), Weisgerber
patent: 4053735 (1977-10-01), Foudos
patent: 4078259 (1978-03-01), Soulsby et al.
patent: 4105156 (1978-08-01), Dethleff
patent: 4107785 (1978-08-01), Seipp
patent: 4153933 (1979-05-01), Blume et al.
patent: 4155071 (1979-05-01), Shamburger
patent: 4382279 (1983-05-01), Ugon

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