High frequency noise and impedance matched integrated circuits

Details High frequency noise and impedance matched integrated circuits High frequency noise and impedance matched integrated circuits

1998-05-29

1999-12-14

Teska, Kevin J.

H01L 27082, G06F 7625, G06F 762

Patent

active

060028602

ABSTRACT:
An monolithic integrated circuit comprising a transistor-inductor structure is provided having simultaneously noise matched and input impedance matched characteristics at a desired frequency. The transistor-inductor structure comprises a first transistor Q.sub.1 which may be a common emitter bipolar transistor or common source MOSFET transistor Q.sub.1, a second optional transistor Q.sub.2, a first inductor L.sub.E in the emitter (source) of Q.sub.1, and a second inductor L.sub.B in the base (gate) of Q1. The emitter length l.sub.E1, or correspondingly the gate width w.sub.g, of Q1 is designed such that the real part of its optimum noise impedance is equal to the characteristic impedance of the system, Z.sub.0, which is typically 50.OMEGA.. The first inductor L.sub.E, provides matching of the real part of the input impedance and the second inductor L.sub.B cancels out the noise reactance and input impedance reactance of the structure. The resulting simultaneously noise and impedance matched integrated circuit provides optimal performance. The optimized transistor-inductor structure has particular application to silicon integrated circuits, such as low noise amplifiers and mixer circuits, for wireless and RF circuit applications at 5.8 Ghz, previously reported only for GaAs based circuits. Other basic silicon integrated circuits were optimized at frequencies up to .about.12 GHz.

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