Semiconductor memory device for high speed data communication ca

Details Semiconductor memory device for high speed data communication ca Semiconductor memory device for high speed data communication ca

1997-01-10

1999-09-21

Canney, Vincent P.

Excavating

G06F 1106

Patent

active

059563494

ABSTRACT:
A memory includes a built-in testing circuit for determining pass/fail of a memory portion and an identifier register for storing identification value for identifying the memory. The memory performs a testing operation according to a command provided from a controller via a send link and sends the result of that testing to a sync link. Thus, the memory controller can identify a defective memory cell. In this way, erroneous operation of the system due to a defective memory cell in a memory system can be prevented.

REFERENCES:
Draft 0.77 IEEE P1596.7-199X "Draft Standard for a High-Speed Memory Interface (SyncLink)", by IEEE Standards Department, Jan. 3, 1996.

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