Dual validity bit arrays

Details Dual validity bit arrays Dual validity bit arrays

1983-04-15

1986-07-22

Shaw, Gareth D.

Excavating

371 67, 364900, G06F 900

Patent

active

046023682

ABSTRACT:
An associative memory used to translate a virtual page number (VPN) of a virtual word address to a physical page number (PPN) of a physical word address of a random access memory of a digital computer system is provided with a pair of independently addressable validity bit arrays, each of which arrays can store a validity bit in each of the addressable locations of each array. A pointer enables only one of the validity bit arrays to receive address signals corresponding to the lower virtual page number (LVPN) of a VPN. The validity bit read out of the memory location corresponding to the LVPN of the enabled array is used in determining if the PPN read out of the corresponding memory location of the associative memory is valid. The bits of the disabled array, immediately after it is disabled, are all reset, or cleared. After all validity bits of the disabled array are reset, a clear associative memory paging (CAMP) instruction can be executed to invalidate all entries written into the associative memory by enabling the cleared disabled array and disabling the array enabled at the time such a CAMP instruction begins execution.

REFERENCES:
patent: 4145738 (1979-03-01), Inoue et al.
patent: 4170039 (1979-10-01), Beacom et al.
patent: 4241401 (1980-12-01), De Wierd et al.
patent: 4326248 (1982-04-01), Hinai et al.
patent: 4374410 (1983-02-01), Sakai et al.

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