Microcomputer addressing system and electronic timepiece utilizi

Details Microcomputer addressing system and electronic timepiece utilizi Microcomputer addressing system and electronic timepiece utilizi

1982-08-20

1986-07-22

Lall, Parshotam S.

Boots, shoes, and leggings

364200, 364705, 364900, 365231, G06F 748

Patent

active

046023470

ABSTRACT:
A microcomputer comprises an address decoder (23) for providing address signals to a random access memory (21). The address decoder (23) is adapted to generate a plurality of address signals in accordance with one piece of instruction data obtained from an instruction register (10). On the other hand, a control circuit (11) is provided for generating change signals in response to the instruction data for controlling a T type flip-flop (24, 25 or 26). The address decoder is responsive to the signal from the T type flip-flop to select and provide one of the plurality of address signals. Accordingly, a plurality of addresses are designated in accordance with one piece of the instruction data, whereby one of them is selected by a change signal. Thus, a program for addressing a random access memory can be simplified. The microcomputer is advantageously employed in an electronic timepiece employing a microcomputer by adapting such that a plurality of pieces of alarm timing data are subjected to the same processing of detection of coincidence with the current time.

REFERENCES:
patent: 4200919 (1980-04-01), Page et al.
patent: 4227247 (1980-10-01), Kintner
patent: 4238832 (1980-12-01), Tsuzuki et al.
patent: 4245323 (1981-01-01), Yamazaki et al.
patent: 4330840 (1982-05-01), Kobayashi
patent: 4348743 (1982-09-01), Dozier
patent: 4408305 (1983-10-01), Kuo
patent: 4415994 (1983-11-01), Ive et al.
patent: 4475176 (1984-10-01), Ishii
patent: 4486847 (1984-12-01), Wattenhofer
"MCS-48 Family of Single Chip Microcomputers User's Manual"; Intel; Sep. 1980.

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