Method of manufacturing master-slice integrated circuit device

Details Method of manufacturing master-slice integrated circuit device Method of manufacturing master-slice integrated circuit device

1983-09-26

1986-07-22

Gruber, Felix D.

Boots, shoes, and leggings

357 40, 364491, H01L 2702, G06F 1560

Patent

active

046023399

ABSTRACT:
A method of manufacturing a master-slice integrated circuit device, implemented based on a total circuit diagram, including one or more logic blocks, each including a plurality of basic logic blocks such as flip-flops, NAND gates, and the like. The total circuit diagram is reformed by deleting unused basic logic blocks in each of the logic blocks whose output terminals are not used, by deleting unused wirings and other unused basic logic blocks whose output terminals are not connected to any basic logic blocks as a result of the deletion of the basic logic blocks, and by sequentially deleting unused basic logic blocks and unused wirings in the same manner, so as to retain only those basic logic blocks actually used as effective basic logic blocks. The circuit patterns of the master slice integrated circuit device are produced by using the total circuit diagram thus reformed.

REFERENCES:
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patent: 4484292 (1984-11-01), Hong et al.
patent: 4500906 (1985-02-01), Ohno et al.
Journal of Digital Systems, "Channel-Order Router-A New Routing Technique for a Masterslice LSI", Kanada et al., vol. IV, Issue 4, pp. 427-441.
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