Return address adding mechanism for use in parallel processing s

Details Return address adding mechanism for use in parallel processing s Return address adding mechanism for use in parallel processing s

1996-02-12

1999-01-05

Auve, Glenn A.

395312, G06F 1300

Patent

active

058571116

ABSTRACT:
When memory access is to be accomplished in a parallel processing system, interfacing between networks is simplified by generating network control information for the return of read out data in the networks and embedding it into requests. For this purpose, flip-flops for identifying input port numbers are provided in each network through which requests are to be transferred, the identified input numbers are embedded into the requests to be transferred and, when returning data, this information is used as network switching control information. Furthermore, the outputs of arbiters in the networks through which requests are transferred are used as input port numbers.

REFERENCES:
patent: 4760518 (1988-07-01), Potash et al.
patent: 4760525 (1988-07-01), Webb
patent: 5179669 (1993-01-01), Peters
patent: 5197130 (1993-03-01), Chen et al.
patent: 5321813 (1994-06-01), McMillen et al.
patent: 5754792 (1998-05-01), Shutoh et al.

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