Apparatus method and system for peripheral component interconnec

Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements

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395306, 345503, 345519, G06F 1300

Patent

active

058570861

ABSTRACT:
A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 32 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 32 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 32 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of a PCI device connected to the common bus.

REFERENCES:
patent: 5682484 (1997-10-01), Lambrecht et al.
patent: 5740387 (1998-04-01), Lambrecht et al.
patent: 5748921 (1998-05-01), Lambrecht et al.
patent: 5754801 (1998-05-01), Lambrecht et al.

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