1997-09-08
1999-01-05
Nguyen, Hoa T.
Excavating
371 275, 371 276, 371 211, G01R 3128
Patent
active
058569855
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a test pattern generator for testing semiconductor memories, and more particularly, to a test pattern generator for testing semiconductor memories having a block write function.
BACKGROUND ART
FIG. 8 shows an example of structure of a conventional semiconductor test system for testing semiconductor devices. The example of FIG. 8 is directed to a situation where the device under test is a semiconductor memory. An address signal is provided to a memory device 2 under test (MUT) from an address generator 12, and a data signal is provided to the memory under test from a data generator 13. A clock control signal which specifies read or write operation is also provided to the memory device from a clock control signal generator 14. After a write operation is completed by applying these signals to the memory device 2 under test, in a read operation, the data read out from the memory device is applied to a logic comparator 3. At the same time, expected value data is provided to the logic comparator 3 from a pattern generator 1. Each of the generators note above is controlled by a sequence controller 11. The pattern generator 1 is comprised of the above mentioned generators and controllers. Furthermore, if necessary, an expected value generator 4 which includes a buffer memory may be provided in the pattern generator to generate expected value data.
In recent years, various types of memory devices to be tested (hereinafter referred to "MUT") have been introduced in the market. For example, there is a type of memory device which has a block write function. Thus, there is a need to test these memory devices which perform complex functions at high speed.
The block write function within the context of the invention is a function to write the data in a block of memory cells, i.e., to write data in a n-bit data register for m words (m.times.n block write) of the MUT by one write cycle. The word number m in the memory to write the data therein is specified by several lower bits of the column address data. For instance, when the lower two bits are used, four words will be specified. Data supplied to a data pin of the MUT in the block write operation is used as word mask data. The data in a mask register in the MUT is used as bit mask data. The data bit or word in the MUT which is not replaced with new data can be independently specified by the mask data.
FIG. 9 is a schematic diagram showing the block of memory cells in the MUT to be accessed by one block write (4.times.4 block write in this example) operation. The block to be accessed by one block write operation is defined by C0, C1, C2, C3, which are designated by decoding the lower two bits of the column address with respect to a corresponding set of plural data bits D0, D1, D2, D3.
FIG. 10 is an example of operation in which it is shown the relationship between each of the data in the sixteen (16) memory cells accessed by the 4.times.4 block write operation. Mask data bits (MD0, MD1, MD2, MD3) are shown in the drawing corresponding to the sixteen (4.times.4=16) memory cells. Data bits (BD0, BD1, BD2, BD3) that are applied to data pins of the MUT are shown in FIG. 10. Further, data register bits (RD0, RD1, RD2, RD3) to be used as write data in the block write operation are shown in FIG. 10. In this example, logic "0" in the mask data is to prevent renewal of the data. Thus, the data in the memory cells shown by slanting lines are prohibited from being written the new data therein, i.e., the data renewal will not take place for the specified memory cells. When reading the data which has been stored through the block write operation, such data is read out word by word like an ordinary reading process of a memory.
In order to test such memory devices having the block write function as described above, expected value data for the test must be generated with regard to the mask data in the word direction and the bit direction. Since the mask operation and the combination of the mask data are complex, the generation of the expected
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patent: 4369511 (1983-01-01), Kimura et al.
patent: 4370746 (1983-01-01), Jones et al.
patent: 4958345 (1990-09-01), Fujisaki
patent: 5453995 (1995-09-01), Behrens
Advantest Corp.
Nguyen Hoa T.
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