Method for preventing sub-threshold leakage in flash memory cell

Details Method for preventing sub-threshold leakage in flash memory cell Method for preventing sub-threshold leakage in flash memory cell

1997-08-05

1999-01-05

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518524, 36518533, G11C 1604, G11C 1606

Patent

active

058569456

ABSTRACT:
The present invention provides a method for preventing sub-threshold leakage in flash EPROM cells during Vt repair, read and verify operations. The present invention prevents sub-threshold leakage by either biasing the floating gate voltage of non-selected cells to a level that is less than the sources voltage. This biasing is achieved by controlling the voltages applied to such non-selected cells bitline and wordline voltages, or by floating the non-selected sourcelines to electrically disconnect the sourcelines of the non-selected cells. This method allows fast and accurate Vt repair of cells while avoiding Vt degradation of non-erased and repaired cells due to subthreshold current leakage, as well as reduced sub-threshold leakage during read and verify operations.

REFERENCES:
patent: 5455792 (1995-10-01), Yi
patent: 5646890 (1997-07-01), Lee et al.
patent: 5682350 (1997-10-01), Lee et al.
patent: 5687121 (1997-11-01), Lee et al.
patent: 5777924 (1998-07-01), Lee et al.

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