Delay locked loop

Details Delay locked loop Delay locked loop

1998-02-20

1999-12-14

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327160, H03L 700

Patent

active

060022817

ABSTRACT:
An apparatus comprising a first circuit configured to receive a first clock signal and delaying the first clock signal by a first delay to generate a second clock signal, the first delay being a first function of a first signal; a phase-frequency detector configured to receive the first clock signal and the second clock signal and generate a second signal dependent on the first delay; a second circuit configured to receive tile second signal and generate a third signal, the third signal being a digital signal; and a current mirror configured to generate the first signal, the first signal being a second function of the third signal.

REFERENCES:
patent: 5629897 (1997-05-01), Iwamoto et al.
patent: 5684421 (1997-11-01), Chapman et al.
patent: 5790612 (1998-08-01), Chengson et al.
patent: 5815016 (1998-09-01), Erickson
patent: 5831465 (1998-11-01), Watarai
patent: 5854797 (1998-12-01), Schwartz et al.

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