Shallow trench isolation process

Details Shallow trench isolation process Shallow trench isolation process

1996-12-31

1999-08-03

Fourson, George

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438437, 438692, H01L 2176

Patent

active

059337486

ABSTRACT:
A shallow trench isolation process provides a high quality oxide on the substrate adjacent the trench and on the upper part of the trench. This process avoids the formation of poor quality oxide on the substrate adjacent the upper edge of the trench that is believed to cause MOS transistors to exhibit the undesirable subthreshold current flow known as the "kink" effect. A pad oxide layer is grown on the surface of a silicon substrate and then a layer of silicon nitride is formed on the surface of the pad oxide. A photoresist mask is formed over the silicon nitride and the silicon nitride and pad oxide are etched, and then the substrate is etched to form a trench. The photoresist mask is removed, a layer of polysilicon is deposited over the silicon nitride layer and within the trench and the polysilicon layer is oxidized. CVD oxide is deposited to overfill the trench and then the excess CVD oxide and polysilicon oxide is removed by CMP, using the silicon nitride layer as an polish stop. The silicon nitride is stripped and the trench oxide is etched using an HF dip to provide a substantially planar surface. A layer of polysilicon is deposited on the device and doping, patterning and etching are used to define wiring lines and gate electrodes from the polysilicon. The polysilicon oxide lining the trench is more durable than the CVD oxide that fills the rest of the trench, and so better protects the substrate near the trench during subsequent etching and polishing steps.

REFERENCES:
patent: 4471525 (1984-09-01), Sasaki
patent: 4493740 (1985-01-01), Komeda
patent: 4666556 (1987-05-01), Fulton et al.
patent: 5294562 (1994-03-01), Lur et al.
patent: 5496765 (1996-03-01), Schwalke
patent: 5521422 (1996-05-01), Mandelman et al.
patent: 5786263 (1998-07-01), Perera
Fuse, G., et al, "A Practical Trench Isolation Technology with a Novel Planarization Process", Semiconductor Research Center, Mitsubishi, 732 IEDM 1987, pp. 732-735, 1987.
Wolf, S., "Silicon Processing for the VLSI Era: vol. 2, Process Integration", Lattice Press, pp. 47-48, 1990.
Wolf, S., "Silicon Processing for the VLSI Era: vol. 3, The Submicron Mosfet". Lattice Press, pp. 371-373, 1995.

Affiliated with

Also associated with

Rating

Shallow trench isolation process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shallow trench isolation process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shallow trench isolation process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-859733