Processor for signal processing and hierarchical multiprocessing

Details Processor for signal processing and hierarchical multiprocessing Processor for signal processing and hierarchical multiprocessing

1988-02-19

1989-07-04

Shaw, Gareth D.

Boots, shoes, and leggings

3649407, G06F 900

Patent

active

048456608

ABSTRACT:
A processor formed from a signal processing unit operating according to instructions transmitted by a bus line, including a slave section provided with an address/data port for connection to a master signal processing circuit; a first buffer register in which data coming from the master processing circuit via the address/data port can be written and read in order to be processed by the processing unit, a second buffer register in which the data processed by the processing unit can be written, then read in order to be directed via the address/data port to the master processing circuit and a sequential control circuit so that access to these buffer registers is allocated in turn to the processing unit and to the master processing circuit. A master section is also provided intended to be connected to at least one slave circuit.

REFERENCES:
patent: 4215395 (1980-07-01), Bunyard et al.
patent: 4224600 (1980-09-01), Sellner
patent: 4498134 (1985-02-01), Hansen et al.

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