Fully testable chip having self-timed memory arrays

Details Fully testable chip having self-timed memory arrays Fully testable chip having self-timed memory arrays

1992-06-12

1995-02-28

Beausoliel, Jr., Robert W.

Excavating

371 223, G11C 2900

Patent

active

053944038

ABSTRACT:
A method and apparatus is provided for testing self timed memory arrays which does not affect the state of cells within the arrays not being tested. Each memory array has a plurality of control, address and data registers which are coupled to the respective control, address and data lines into the memory array. A timing generator circuit receives an external clock pulse and provides the self-timed clock pulses to the memory array. During the shift mode, the control, address and data registers are chained together such that data for testing can be scanned serially into the registers. In order to prevent unplanned array modification operations from occurring during the shift mode because a bit shifted into the write-enable or clear register at the time a clock pulse derived from the timing circuitry is generated, a logic means is provided to disable all clock pulses during the shift mode. A separate shift clock pulse is provided during shift mode to shift the test information into the control, address and data registers. Once the information is shifted in, a separate test clock pulse is issued to cause the operation indicated by the data in the address, control and data registers to be performed. Thus, the operation identified by the control address and data registers is performed without affecting the state of the control registers of adjacent memory arrays and without affecting the state of other memory cells and components on the chip while maintaining the same temporal state of the chip.

REFERENCES:
patent: 3970993 (1976-07-01), Finnila
patent: 4355377 (1982-10-01), Sud et al.
patent: 4701921 (1987-10-01), Powell et al.
patent: 4833676 (1989-05-01), Koo
patent: 5029133 (1991-07-01), La Fetra et al.
patent: 5031141 (1991-07-01), Guddat et al.
patent: 5124589 (1992-06-01), Shiomi et al.

Affiliated with

Also associated with

Rating

Fully testable chip having self-timed memory arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fully testable chip having self-timed memory arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fully testable chip having self-timed memory arrays will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-853715