Data processing system generating clock signal from an input clo

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364271, 364270, 3642703, 3642716, 364DIG1, 307269, 331 1A, G06F 112

Patent

active

051330644

ABSTRACT:
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

REFERENCES:
patent: 3758720 (1973-09-01), Dinn
patent: 3829790 (1974-08-01), Macrander
patent: 3961269 (1976-06-01), Alvarez
patent: 4468634 (1984-08-01), Takagi
patent: 4486850 (1984-12-01), Hyatt
patent: 4504745 (1985-03-01), Spence
patent: 4521893 (1985-06-01), Bellman
patent: 4590439 (1986-05-01), Goggin
patent: 4630193 (1986-12-01), Kris
patent: 4644498 (1987-02-01), Bedard
patent: 4673891 (1987-06-01), Remy
patent: 4677394 (1987-06-01), Vollmer
patent: 4689581 (1987-08-01), Talbot
patent: 4754164 (1988-06-01), Flora
patent: 4774686 (1988-09-01), McClary
patent: 4779008 (1988-10-01), Kessels
patent: 4829545 (1989-05-01), Guzik
patent: 4847516 (1989-07-01), Fujita
patent: 4862104 (1989-08-01), Muratani
patent: 4864253 (1989-09-01), Zwack
patent: 4893271 (1990-01-01), Davis
patent: 4906944 (1990-03-01), Frerking
Design of PLL-Based Clock Generation Circuits, by Deog-Kyoun Jeong et al., IEEE Journal of Solid State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.
A Synchronous Approach for Clocking VLSI Systems, (IEEE Journal of Solid State Circuits), vol. SC-17, No. 1, Feb. 1982, pp. 51-56.
A 130 k-Gate CMOS Mainframe Chip Sets ISSCC 87, Session VIII, pp. 86-87.
A ISMIPS 32b Microprocessors 2SSCC 87 Section II, pp. 26-27.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Data processing system generating clock signal from an input clo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data processing system generating clock signal from an input clo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing system generating clock signal from an input clo will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-851399

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.