Method for making closely spaced stacked capacitors on DRAM chip

Details Method for making closely spaced stacked capacitors on DRAM chip Method for making closely spaced stacked capacitors on DRAM chip

1994-03-21

1995-01-10

Fourson, George

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

053806751

ABSTRACT:
A method for fabricating an array of closely spaced storage capacitors, with increased capacitance, on a dynamic random access memory (DRAM) chip is achieved. The capacitors are increased in capacitance by minimizing the spacings between the adjacent bottom electrodes of the storage capacitors and, thereby increases the area of the capacitor electrodes. A local oxidation techniques is used to form a silicon oxide etch mask, on the bottom electrode polysilicon layer, that extends laterally under a patterned silicon nitride masking layer. This encroachment of the silicon oxide under the patterned silicon nitride layer reduces the spacing between electrodes, exceeding the resolution limits of the photoresist. The silicon nitride is removed and the silicon oxide mask is used to pattern the polysilicon layer forming an array of closely spaced polysilicon bottom electrodes. The silicon oxide is removed and an inter-electrode dielectric is deposited on the array of bottom electrode. A second doped polysilicon layer is then deposited to form the top electrode and complete the DRAM capacitors.

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"A Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256 Mbit DRAM" by T. Eimori et al, IEEE International Electron Device Meeting Proceedings, Dec. 1993, pp. 631-634.

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