Erasure of eeprom memory arrays to prevent over-erased cells

Details Erasure of eeprom memory arrays to prevent over-erased cells Erasure of eeprom memory arrays to prevent over-erased cells

1990-04-16

1992-07-21

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 700

Patent

active

051329352

ABSTRACT:
The device and process of this invention provide for eliminating reading errors caused by over-erased cells by subsequently applying alternating erasing and programming pulses to the cells of an EEPROM array, starting with relatively high-energy-level erasing and programming voltages, decreasing the energy-level of each of the alternating erasing and programming voltages. The initial, relatively high-energy-level pulses should have sufficient energy to cause all of the cells to be programmed and to cause all of the cells to be over-erased. The energy-levels are decreased until electron transfer between floating gate and a source or drain region ceases. As the energy-levels are decreased, the threshold voltage range of the memory cells is compacted. The final threshold voltages are distributed within a preselected narrow range of positive values that are less than a predetermined wordline select voltage.

REFERENCES:
patent: 4888738 (1989-12-01), Wong et al.

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