Low power, process and temperature insensitive FET bias circuit

Details Low power, process and temperature insensitive FET bias circuit Low power, process and temperature insensitive FET bias circuit

1981-08-06

1984-05-15

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307580, 307571, H03K 1714, H03K 17687

Patent

active

044490674

ABSTRACT:
A bias circuit for an FET switch in which a pinch-off voltage is generated and sets up a current through a first resistor. The current is reflected through a second resistor to establish a voltage differential across the second resistor which is then imposed across the gate-source terminals of the switch FET when it is desired to turn the switch OFF. The relationship of the turn-off voltage imposed across the switch FET to its pinch-off voltage is determined by the ratio of the resistance values of the two matched resistors, which ratio is independent process and temperature. The switch bias circuit thus offers highly reliable operation and at the same time a greatly reduced power consumption.

REFERENCES:
patent: 3955103 (1976-05-01), Russell et al.
patent: 4228367 (1980-10-01), Brown
patent: 4323796 (1982-04-01), Lathrope
Adib R. Hamade and Jose F. Albarran, "A JFET/Bipolar 8-Channel Analog Multiplexer," I.E.E.E. Journal of Solid State Circuits, Dec. 1975, pp. 399-406.
Data Sheet for SSS7510/7511 Quad SPST BI-FET Analog Switch.

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