Low inductance side mount decoupling test structure

Details Low inductance side mount decoupling test structure Low inductance side mount decoupling test structure

1990-11-30

1992-07-21

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 731, 361414, G01R 3102, G01R 3128, H05K 100

Patent

active

051326132

ABSTRACT:
An integrated circuit test structure is comprised of a stacked substrate MLC space transformer (5). A top surface of an interface substrate (12) is employed for decoupling capacitor (36) placement. The top surface has metal conductors (20) exposed thereon for terminating power supply buses from a tester (1). Individual layers of a personalization substrate (14) are fabricated to redundantly extend internal power plane metalization (22) to the sidewalls. Redundant pads (26) are placed on each personalization layer to increase the surface area for side mount contact. Metal pads (18) are deposited over the exposed sidewall metal for forming a sidewall contact to the power planes within the personalization substrate. The personalization substrate is joined to the upper surface of the interface substrate and the sidewall contacts are conductively coupled by conductive members (40) to the interface substrate metal conductors (20), thereby providing a low inductance, low resistance DC path from the tester to a device under test (4). The decoupling capacitors are electrically coupled to the metal lines in close proximity the personalization substrate thereby minimizing the associated lead inductance and maximizing the effectiveness of the decoupling capacitors.

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