Fishing – trapping – and vermin destroying
Patent
1991-01-28
1992-07-21
Quach, T. N.
Fishing, trapping, and vermin destroying
437 41, 437228, 437193, 437 50, 437 67, H01L 21336
Patent
active
051322374
ABSTRACT:
A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members which are electrically isolated from the first polysilicon members. Impurities are diffused from the polysilicon members into the substrate to form the source/drain regions of the MOS transistors, and the extrinsic base and emitter regions of the NPN transistors. The final processing steps include those required for the interconnection of the MOS and NPN transistors.
REFERENCES:
patent: 4707456 (1987-11-01), Thomas et al.
patent: 4727046 (1988-01-01), Tuntasood et al.
patent: 4735916 (1988-04-01), Homma et al.
patent: 4784971 (1988-11-01), Chin et al.
patent: 4816423 (1988-10-01), Havermann
patent: 4826783 (1988-11-01), Choi et al.
patent: 4902640 (1990-02-01), Sachitano et al.
patent: 4945070 (1990-07-01), Hsu
MicroUnity Systems Engineering, Inc.
Quach T. N.
LandOfFree
Planarization method for fabricating high density semiconductor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Planarization method for fabricating high density semiconductor , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Planarization method for fabricating high density semiconductor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-842883