Monolithically integrated testable registers that cannot be dire

Details Monolithically integrated testable registers that cannot be dire Monolithically integrated testable registers that cannot be dire

1986-12-22

1988-08-23

Fleming, Michael R.

Excavating

371 25, G01R 3128

Patent

active

047665939

ABSTRACT:
A circuit is provided for testing a plurality of non-readable latch registers. Each of a plurality of first logic gates have an input coupled to one of a plurality of input pins, and an output coupled to an input of each of the latch registers. An address circuit is coupled to the latch registers for selectively addressing one of the latch registers. A plurality of second logic gates each have an input coupled to one output of each of the latch registers and an output coupled to one of the input pins. An enabling circuit is coupled to each of the second logic gates for enabling the logic gates.

REFERENCES:
patent: 4403287 (1983-09-01), Blahul
patent: 4594544 (1986-06-01), Necoechea
patent: 4710933 (1987-12-01), Powell

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