Vector processor which can be formed by an integrated circuit of

Details Vector processor which can be formed by an integrated circuit of Vector processor which can be formed by an integrated circuit of

1991-10-30

1993-08-24

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 36423221, 36493151, G06F 15347

Patent

active

052396606

ABSTRACT:
In a vector calculation unit (31), a multiplication and an addition result register (50 and 53) are connected to a pipeline multiplier (14) and a pipeline adder (15), respectively. A multiplication and an addition result bus (52 and 55) are connected to the multiplication and the addition result registers, respectively. A selector (S1) connects one of an input bus (11) and the multiplication and the addition result buses to the first operand register to which a first multiplication and a first addition operand bus (44 and 45') are connected. A selector (S2) connects one of another input bus (12) and the multiplication and the addition result buses to the second operand register to which second multiplication and second addition operand buses (48 and 49) are connected. A selector (S3) connects one of the first multiplication operand, the multiplication result, and the addition result buses to an input of the multiplier. A selector (S4) connects one of the second multiplication operand, the multiplication result, and the addition result buses to another input of the multiplier. A selector (S5) connects one of the first addition operand, the multiplication result, and the addition result buses to an input of the adder. A selector (S6) connects one of the second addition operand, the multiplication result, and the addition result buses to another input of the adder. A selector (S7) connects one of the first addition operand, the second addition operand, the multiplication result, and the addition result buses to an output bus (13).

REFERENCES:
patent: 4302818 (1981-11-01), Niemann
Computer Architecture and Parallel Processing, Hwang et al., McGraw-Hill, pp. 263-271.

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