Arrangement for reducing computer power consumption by turning o

Details Arrangement for reducing computer power consumption by turning o Arrangement for reducing computer power consumption by turning o

1991-02-04

1993-08-24

Harrell, Robert B.

Boots, shoes, and leggings

364707, 364DIG1, 3642731, 364241, G06F 1500, G06F 1130

Patent

active

052396525

ABSTRACT:
A power consumption reduction method and apparatus for a computer is described. The operating system running on the CPU of the computer determines when the CPU is not actively processing and generates a power-off signal to a control logic circuit. The control logic circuit then disconnects the CPU from the power supply. Pulses sent by a periodic timer or interrupts from input/output units are applied to the control logic circuit to at least periodically issue a power-on signal to the CPU. Power is supplied to the CPU for a given time period at every power-on signal. During this period, the CPU executes miscellaneous housekeeping chores including the polling of disk drives and determines when the CPU should resume normal processing. The control logic circuit also determines, at every power-on signal, whether the CPU is already on or being turned off. The control logic circuit will not issue a reset signal to enable the reset of the CPU if it is already on. If, however, the CPU has been turned off by the operating system, the control logic circuit will reset the CPU at every periodic power-on signal until CPU resumes its normal operation.

REFERENCES:
patent: 4698748 (1987-10-01), Juzswik et al.
patent: 4769768 (1988-09-01), Bomba et al.
patent: 4809163 (1989-02-01), Hirosawa et al.
patent: 4851987 (1989-07-01), Day
patent: 4870570 (1989-09-01), Satoh et al.
patent: 4965738 (1990-10-01), Bauer et al.
patent: 5142684 (1992-08-01), Perry et al.

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