Logic circuit arrangement employing insulated gate field effect

Details Logic circuit arrangement employing insulated gate field effect Logic circuit arrangement employing insulated gate field effect

1974-08-23

1976-03-09

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307207, 307208, 307215, H03K 1908, H03K 1934, H03K 1936

Patent

active

039433773

ABSTRACT:
A logic circuit arrangement consisting of insulated gate field effect transistors of opposite channel types wherein the drain electrode of a single first insulated gate field effect transistor of one channel type is connected to the drain electrode of at least one second insulated gate field effect transistor of the opposite channel type constituting a logic gate. The gate electrode of second transistor is supplied with a data signal and the gate electrode of first transistor and the source electrode of second transistor are supplied with clock pulse signals bearing a complementary relationship with each other. The source electrode of first transistor may receive a clock pulse signal supplied to the source electrode of second transistor or constant voltage; and an output signal from the logic circuit is delivered from the junction of the first and second transistors.

REFERENCES:
patent: 3250917 (1966-05-01), Hofstein
patent: 3518451 (1970-06-01), Booher
patent: 3524077 (1970-08-01), Kaufman
patent: 3551693 (1970-12-01), Burns et al.
patent: 3601627 (1971-08-01), Booher
patent: 3626202 (1971-12-01), Pound
patent: 3747064 (1973-07-01), Thompson
patent: 3870897 (1975-03-01), Hatsukano et al.

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