Patent
1997-09-09
1999-12-07
Lee, Thomas C.
39520077, 395500, B06F 1300
Patent
active
059997435
ABSTRACT:
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST.
REFERENCES:
patent: 4126894 (1978-11-01), Cronshaw et al.
patent: 4400794 (1983-08-01), Koos
patent: 4775931 (1988-10-01), Dickie et al.
patent: 5348921 (1994-09-01), Lambrecht et al.
patent: 5392407 (1995-02-01), Heil et al.
patent: 5479627 (1995-12-01), Khalidi et al.
patent: 5506997 (1996-04-01), Maguire et al.
patent: 5546555 (1996-08-01), Horstmann et al.
patent: 5555383 (1996-09-01), Elazar et al.
patent: 5596729 (1997-01-01), Lester et al.
patent: 5623691 (1997-04-01), Clohset et al.
patent: 5644224 (1997-07-01), Davis
patent: 5664161 (1997-09-01), Fukushima et al.
patent: 5678064 (1997-10-01), Kulik et al.
patent: 5682484 (1997-10-01), Lambrecht et al.
patent: 5717873 (1998-02-01), Rabe et al.
patent: 5721839 (1998-02-01), Callison et al.
patent: 5734847 (1998-03-01), Garbus et al.
patent: 5740381 (1998-04-01), Yen
patent: 5740387 (1998-04-01), Lambrecht et al.
patent: 5740409 (1998-04-01), Deering
patent: 5754801 (1998-05-01), Lambrecht et al.
patent: 5754807 (1998-05-01), Lambrecht et al.
patent: 5761458 (1998-06-01), Young et al.
patent: 5768612 (1998-06-01), Nelson
patent: 5771359 (1998-06-01), Gallaway et al.
patent: 5790831 (1998-08-01), Lin et al.
patent: 5796963 (1998-08-01), Odom
patent: 5802568 (1998-09-01), Csoppenszky
patent: 5812789 (1998-09-01), Diaz et al.
patent: 5832262 (1998-11-01), Johnson et al.
patent: 5835760 (1998-11-01), Harmer
patent: 5835962 (1998-11-01), Chang et al.
Halfhill, "Unclogging The PC Bottlenecks", Byte Sep. '97, vol. 22, No. 9.
Yong, "AGP Speeds 3D Graphics" Microprocessor Report, Jun. 17, 1996.
Brummer, "PCI-To-AGP Move Boosts 3-D Graphics" Electronic Engineering Times, 1997, N952, p. 84.
Elliot Robert C.
Horan Ronald T.
Jones Phillip M.
Lester Robert Allan
Santos Gregory N.
Chichester Ronald L.
Compaq Computer Corporation
Elamin Abdelmoniem I.
Katz Paul N.
Lee Thomas C.
LandOfFree
System and method for dynamically allocating accelerated graphic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for dynamically allocating accelerated graphic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for dynamically allocating accelerated graphic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-834295