Dual latch data transfer pacing logic using a timer to maintain

Details Dual latch data transfer pacing logic using a timer to maintain Dual latch data transfer pacing logic using a timer to maintain

1995-01-26

1999-12-07

Sheikh, Ayaz R.

395821, 395845, 395878, 395877, 395881, 395550, G06F 1300

Patent

active

059997427

ABSTRACT:
A dual latch character pacing circuit on a semiconductor chip controls data transfer between a pair of microprocessor which have significantly different data transfer rates. A first and second latch are connected in a parallel data path between the two microprocessor. The timing circuit includes a flip-flop which clocks the data between the latches. A one-shot timer is re-started on each transfer of data thereby insuring that the rate of transfer is substantially constant over a character period.

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Microcom DeskPorte Fast Reference Manual, Chpt. 3, p. 27.

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