Circuit delay optimizing using circuit arrangement, layout infor

Details Circuit delay optimizing using circuit arrangement, layout infor Circuit delay optimizing using circuit arrangement, layout infor

1997-03-28

1999-12-07

Teska, Kevin J.

39550011, G06F 1700

Patent

active

05999715&

ABSTRACT:
A circuit delay optimizing apparatus, includes an information input unit with a logic synthesizer unit that receives, from a layout unit, layout information after completion of layout of a circuit to be changed and wiring and wiring delay information represented by wiring capacitances and fan-out numbers of individual wiring lines. A circuit change portion searching unit searches the layout information to determine a circuit change on the basis of the wiring delay information. Wiring delay information after a circuit change is determined with respect to the change portion of the circuit, through a predetermined technique. A wiring capacitance after the circuit change is calculated by using a function of a fan-out number after the circuit change, a fan-out number before the circuit change and a wiring capacitance before the circuit change. A wiring delay time is calculated from the calculated wiring capacitance by using a predetermined function and the calculated delay time is used to determine if it is an improvement over the delay time before the circuit change. A circuit changing unit changes the circuit change portion only after an improvement is determined.

REFERENCES:
patent: 5003487 (1991-03-01), Drumm et al.
patent: 5461576 (1995-10-01), Tsay et al.
patent: 5629860 (1997-05-01), Jones et al.
patent: 5689432 (1997-11-01), Blaauw et al.
Ramachandran et al "Combined Topological and Functionality-Based Delay Estimation Using a Layout-Driven Approach for High-Level Applications," IEEE, pp. 1450-1460, Dec. 1994.
"Design Compiler Family Reference Manual", published by Synopsys Company in the U.S., pp. 8-21-8-26, 1995.

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