High performance track/hold for a digital multimeter

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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Details

307264, 3072965, 341122, 328127, 328151, H03K 5159, H03L 500

Patent

active

049221302

ABSTRACT:
A track/hold circuit having a holding capacitor whose voltage is replicated by a non-inverting unity gain output amplifier combines both high-speed operation and compensation for errors affecting linearity. The holding capacitor is coupled to the input voltage through two junction field effect transistors (JFET's) that are in series. Both JFET's are on when the circuit is in TRACK. To switch from TRACK to HOLD the JFET nearest the holding capacitor is switched off before the JFET nearest the input voltage. A first source of pedestal error in the output voltage from the output amplifier is rendered constant and well behaved, so that it may be calibrated out. This rendering is accomplished by limiting the voltage swing on the gate of the JFET nearest the holding capacitor to be between the input voltage itself (when that JFET is on) at one extreme and a fixed voltage offset from the input voltage (when that JFET is off) at the other extreme. The fixed voltage offset from the input voltage is derived from the output voltage, which normally equals the input voltage. Feed-through errors and a second source of pedestal error are eliminated by a third FET coupled between the junction of the first two and the output voltage. The third FET is off during TRACK and on during HOLD. The three FET's are switched in a particular order to transition from TRACK to HOLD.

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patent: 4651034 (1987-03-01), Sato
patent: 4687998 (1989-08-01), Takatori et al.

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