Low-latency, high-throughput, integrated cache coherent I/O syst

Details Low-latency, high-throughput, integrated cache coherent I/O syst Low-latency, high-throughput, integrated cache coherent I/O syst

1996-06-06

1999-03-16

Barry, Esq., Lance Leonard

395878, 395881, 395551, 395559, G06F 1300

Patent

active

058841008

ABSTRACT:
A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer. In one embodiment, the integrated I/O system contains a dedicated memory management unit including a translation lookaside buffer which converts I/O addresses to physical addresses for the processing core.

REFERENCES:
patent: 3715729 (1973-02-01), Mercy
patent: 4873703 (1989-10-01), Crandall et al.
patent: 4932040 (1990-06-01), Barlow
patent: 5276842 (1994-01-01), Sugita
patent: 5305452 (1994-04-01), Khan et al.
patent: 5434996 (1995-07-01), Bell
patent: 5444860 (1995-08-01), Datwyler et al.
patent: 5459851 (1995-10-01), Nakajima et al.
patent: 5524270 (1996-06-01), Haess et al.
patent: 5537581 (1996-07-01), Conary et al.
patent: 5630107 (1997-05-01), Carmean et al.
patent: 5659711 (1997-08-01), Sugita
M. Morris Mano, Comuter System Architecture (3rd ed. 1993), pp. 415-420, 446, 476-483, 1993.

Affiliated with

Also associated with

Rating

Low-latency, high-throughput, integrated cache coherent I/O syst does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-latency, high-throughput, integrated cache coherent I/O syst, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-latency, high-throughput, integrated cache coherent I/O syst will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-826027