SOI layout for low resistance gate

Details SOI layout for low resistance gate SOI layout for low resistance gate

1991-05-29

1992-01-07

James, Andrew J.

357 4, 357 45, 357 56, 357 59, H01L 2701, H01L 2712, H01L 2710, H01L 2906

Patent

active

050796046

ABSTRACT:
Silicon-on-insulator mesa steps cause high resistance in polycrystalline material because of the lack of silicide coverage. In a gate or word line, for instance, this accounts for a large resistance. By connecting the mesas through the body nodes of adjacent transistors, all mesa steps in a polycrystalline semiconductor gate are eliminated. Thus, gate or word line resistance is reduced.

REFERENCES:
patent: 4809044 (1989-02-01), Pryor et al.
patent: 4809056 (1989-02-01), Shirato et al.
patent: 4899202 (1990-02-01), Blake et al.
patent: 4905062 (1990-02-01), Esquivel et al.
patent: 4914491 (1990-04-01), Yu
patent: 4918498 (1990-04-01), Plus et al.

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