Logic circuit apparatus and method for sequentially performing o

Details Logic circuit apparatus and method for sequentially performing o Logic circuit apparatus and method for sequentially performing o

1996-11-05

1999-03-16

Lall, Parshotam S.

Boots, shoes, and leggings

39518309, 364578, G06F 1750

Patent

active

058840656

ABSTRACT:
In a fault simulator for simulating a logic circuit model which is operable in response to first through n-th input pattern signals, a signal generating circuit implemented by hardware generates the first through the n-th input pattern signals. The logic circuit model is assorted into first through m-th levels and is defined by first through p-th faults. The fault simulator carries out a plurality of simulations at the same time in each of the first through the m-th levels. When the simulation proceeds to the m-th level, the fault simulator produces a simulation result signal representative of detected faults and a correct value. The fault simulator simulates the first through the p-th faults by the use of each of the first through the n-th input pattern signals.

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Breuer et al., "Diagnosis and Reliable Design of Digital Systems", Chapter 2, pp. 25-162 and 224-241.

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