Unified multi-function operation scheduler for out-of-order exec

Details Unified multi-function operation scheduler for out-of-order exec Unified multi-function operation scheduler for out-of-order exec

1996-05-16

1999-03-16

Ellis, Richard L.

395586, G06F 900

Patent

active

058840591

ABSTRACT:
A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to operations to be executed, being executed, or completed. The scheduler issues operations to execution units for parallel pipelined execution, selects and provides operands as required for execution, and acts as a reorder buffer keeping the results of operations until the results can be safely committed. The scheduler is tightly coupled to execution pipelines and provides a large parallel path for initial operation stages which minimize pipeline bottlenecks and hold ups into and out of the execution units. The scheduler monitors the entries to determine when all operands required for execution of an operation are available and provides required operands to the execution units. The operands selected can be from a register file, a scheduler entry, or an execution unit. Control logic in the entries is linked together into scan chains which identify operations and operands for execution.

REFERENCES:
patent: 4807115 (1989-02-01), Torng
patent: 5136697 (1992-08-01), Johnson
patent: 5454117 (1995-09-01), Puziol et al.
patent: 5519864 (1996-05-01), Martell et al.
patent: 5530816 (1996-06-01), Holt
patent: 5546597 (1996-08-01), Martell et al.
patent: 5555432 (1996-09-01), Hinton et al.
patent: 5560025 (1996-09-01), Gupta et al.
patent: 5761776 (1996-10-01), Popescu et al.
patent: 5858176 (1989-08-01), Wilhite et al.
Dwyer III, Harry, A Multiple, Out-of-Order, Instruction Issuing System for Superscalar Processors, Cornell University, Chapter 8:212-233. Aug. 1991.
Dwyer, A Multiple, Out-of-Order, Instruction Issuing System for Superscalar Processors, Chapter 3: Fast Dispatch Stack, Aug., 1991, pp. 30-73.
Popescu, V., et al., "The Metaflow Architecture", 1 Jun. 1991, pp. 10-13, 63-73, IEEE Micro., vol. 11, No. 3, XP000237231.
Torng, H. C., et al., "On Instruction Windowing for Fine Grain Parallelism in High-Performance Processors", 23 Mar. 1993, pp. 98-104, IEEE, XP000370465.
Pickett, J. K., et al., "Enhanced Superscalar Hardware: The Schedule Table", 15 Nov. 1993, pp. 636-644, IEEE, XP000437401.
Sohi, G.S., "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers", 1 Mar. 1990, pp. 349-359, IEEE Transactions on Computers, vol. 39, No. 3, XP000103439.
Capozzi, A.J., et al., "Non-Sequential High-Performance Processing", Oct., 1984, pp. 2842-2844, IBM Technical Disclosure Bulletin, XP002024299.

Affiliated with

Also associated with

Rating

Unified multi-function operation scheduler for out-of-order exec does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Unified multi-function operation scheduler for out-of-order exec, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Unified multi-function operation scheduler for out-of-order exec will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-825388