Odd number frequency division with symmetrical output

Details Odd number frequency division with symmetrical output Odd number frequency division with symmetrical output

1981-08-18

1983-08-16

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Starting, stopping, presetting or resetting the counter

Counter chains with a radix or base other than the number...

377116, 377119, H03K 2136, H03K 2324

Patent

active

043995497

ABSTRACT:
A method and apparatus is described for dividing a clock frequency by any odd number to obtain a symmetrical output. Generally, some dividers in a chain of divide-by-two dividers are designated as controlled dividers and others are designated as uncontrolled dividers. The clock input of each controlled divider receives the output of an exclusive NOR gate, the inputs to which include the output of the last divider in the chain and either the clock signal or the output of a preceding divider, depending on certain criteria. The clock input of each uncontrolled divider receives the output of an immediately preceding divider. With this arrangement, the last divider in the chain develops a divided output which is symmetrical.

REFERENCES:
patent: 3873815 (1975-03-01), Summers
patent: 3902125 (1975-08-01), Oliva, Jr.
patent: 3906374 (1975-09-01), Fletcher et al.
patent: 3943379 (1976-03-01), McGuffin
patent: 3967205 (1976-06-01), Rossi et al.
Article entitled "Divide Symmetrical Clock Pulses by Odd Numbers, Get a Symmetrical Output", p. 110 of the Mar. 1, 1980 Edition of Electronic Design.

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