Two-transistor programmable memory cell with a vertical floating

Details Two-transistor programmable memory cell with a vertical floating Two-transistor programmable memory cell with a vertical floating

1990-06-29

1992-01-07

James, Andrew J.

357 235, 357 236, H01L 2910, H01L 2978

Patent

active

050784986

ABSTRACT:
A two-transistor programmable memory cell (FIG. 1A, 20) with one vertical floating gate transistor (VT) and one planar transistor (PT)--the planar transistor can be optimized for programming with low current (longer channel length and narrower channel width), while the vertical transistor can be optimized for reading with high current (shorter channel length and wider channel width). The vertical transistor is formed in a trench (22) with a source region (15) and a sub-source VT drain region (23). The planar transistor includes the source region (15) and a co-planar PT drain region (27).

REFERENCES:
patent: 4774556 (1988-09-01), Fujii et al.
patent: 4835741 (1989-05-01), Baglee
patent: 4929988 (1990-05-01), Yoshikawa
patent: 4964080 (1990-10-01), Tzeng

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