Preemptive multithreading computer system with clock activated i

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G06F 946

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active

056946040

ABSTRACT:
A multithreading computer system provides concurrent asynchronous preemptive time-sliced execution of a plurality of threads of instructions located within the same software program. A clock or timer periodically activates the interrupt operation of the central processor. Each interrupt preempts an executing thread after the thread has executed for a brief timeslice during which the thread may have performed only a portion of its task. Control of the processor is thereby taken away from the preempted thread, and control then passes to an interrupt service routine which then passes control to another thread to invoke the latter for execution during the next timeslice. Control is thereafter returned to the preempted thread to enable the latter to resume execution at the point where it was previously interrupted. Control of the processor is thus transferred repeatedly back and forth between the threads so rapidly that the threads are run substantially simultaneously. The threads may thus execute incrementally and piecewise with their successive task portions executed alternately in a mutually interleaved relation and with each thread executed during its respective series of spaced timeslices interleaved with the timeslices of at least one other thread.

REFERENCES:
Cheriton, David Ross, "Multi-Process Structuring and the Thoth Operating System," Doctorial Thesis, University of Waterloo, 1978.
Lorin, Harold, "Parallelism in Hardware and Software, Real and Apparent Concurrency," Prentice-Hall Inc., 1972, p. 43.
Cheriton et al., "Thoth, a Portable Real-Time Operating System," Department of Computer Science, University of Waterloo, Mar. 1978.
Hiromoto, Robert, Parallel-processing a large scientific problem, AFIPS Press. 1982, pp. 235-237.
Ousterhout, John K., Scheduling techniques for Concurrent Systems, IEEE, 1982, pp. 22-30.
Andrews, Gregory R., Synchronizing Resources, ACM Transactions on Programming Languages and Systems, vol. 3, No. 4, Oct. 1981, pp. 405-430.
Colin, A.J.T., The Implementation of STAB-1, Software -Practice and Experience, vol. 2, 1972, pp. 137-142.
Artym, Richard, The STAB Multiprocessing Environment for CYBA-M, Software -Practice and Experience, vol. 12, 1982, pp. 323-329.
Treleaven et al., Combining Data Flow and Control Flow Computing, The Computer Journal, vol. 25, No. 2, 1982, pp. 207-217.
Duffie, C. A. III, Task Scheduling Algorithm for a Teleprocessing Communications Controller, IBM Technical Disclosure Bulletin, vol. 16, No. 10, Marcy 1974, pp. 3349-3352.
Hoare, C. A. R., Towards a Theory of Parallel Programming, Operating Systems Techniques, Proceedings of a Seminar held at Queen's University, Belfast, 1972, Aademic Press, 1972, pp. 61-71.

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