Method and apparatus for determining the dispatch readiness of b

Details Method and apparatus for determining the dispatch readiness of b Method and apparatus for determining the dispatch readiness of b

1995-07-27

1997-12-02

Harrell, Robert B.

G06F 1200, G06F 930

Patent

active

056945531

ABSTRACT:
The present invention provides a buffer management scheme for load operations that permits load operations to be stored for execution to memory. The buffer management scheme of the present invention calculates the readiness of multiple buffered load operations to speed up dispatch of at least one of the load operations to memory. By providing such management, the present invention allows memory operations and their execution by a device, such as a processor, to be coordinated with the operation of the system and other operations in the processor.

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Johnson, Mike; Superscalar Microprocessor Design; Prentice Hall, Inc., New Jersey, 1991.

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