Boots – shoes – and leggings
Patent
1991-02-21
1993-05-18
Trans, Vincent N.
Boots, shoes, and leggings
364490, 364489, 364488, G06F 1560
Patent
active
052126536
ABSTRACT:
A method for producing layout comprises the steps of: producing power line and other blocks according to inputted circuit configuration data represent kind, attribute data and element to be included in the semiconductor integrated circuit; determining kind of element portions arranged at each of the blocks according to the total area of each kind of the element portion in each block; moving the different kind of element portion in each block to one of blocks including the same kind of element portion; and arranging the element portions according to the data of a horizontal position. For obtaining a vertical length of each block, a minimum lengths of resistor and capacitor blocks are inputted; then the actual vertical length of the transistor block is determined; and then final vertical lengths of resistor and capacitor blocks are determined. A resistor or capacitor is modified in its shape if it has large length than the determined vertical length. A resistor or capacitor with large area is made with full vertical length of the layout. Other components are arranged between full vertical length blocks.
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Matsushita Electronics Corporation
Trans Vincent N.
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