Process of making a double heterojunction 3-D I.sup.2 L bipolar

Details Process of making a double heterojunction 3-D I.sup.2 L bipolar Process of making a double heterojunction 3-D I.sup.2 L bipolar

1986-08-01

1988-09-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 55, 437106, 437131, 437174, 437110, 437111, 437200, 148DIG11, 148DIG12, 148DIG142, 148DIG147, 148DIG160, 148DIG164, 148DIG169, 156613, 156614, 357 34, 357 56, 357 92, H01L 2704, H01L 2120

Patent

active

047710136

ABSTRACT:
A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus. Another method is by constructing guest and host wafers, each containing respective portions of the strata, and fusing said guest and host wafers together.

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