Data processor implementing a two's complement addressing techni

Details Data processor implementing a two's complement addressing techni Data processor implementing a two's complement addressing techni

Filed on

1993-07-08

Date issued

1994-07-05

Examiner

Rudolph, Rebecca L.

Patent Class

Boots, shoes, and leggings

Other Related Categories

364955, 3649552, G06F 934, G06F 1200

Type

Patent

Status

active

Patent number

053275420

Description

ABSTRACT:
The data processor related to the invention accesses memory with an address value which is expressed by signed binary notation expressed by twos compliment, is so constructed that the negative address value having maximum absolute value and the positive address value having the same are not wrapped around each other, is provided with hardware which signed extends the address values expressed by relatively small bit number, and is so constructed that the user area and the supervisor area are separated from each other in accordance with the positiveness and the negativeness of address value, so that the positive and negative address space are allowed to optionally be extended in the direction of the greater absolute value without being split, and extending process of address value is easy, furthermore, the user area and the supervisor area can be judged merely by means of the signed bit denoting either the positiveness or the negativeness, to thereby violation of the access right in the supervisor area under the user mode being able to easily be detected.

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