Fishing – trapping – and vermin destroying
Patent
1996-02-28
1997-12-02
Trinh, Michael
Fishing, trapping, and vermin destroying
437 2, 437228, 437921, H01L 2177
Patent
active
056935455
ABSTRACT:
A method for forming a semiconductor sensor FET device (2) comprises the steps of forming spaced-apart doped source (6) and drain (8) regions in a semiconductor substrate (4) with electrically conductive paths (16, 18) to each region. The region between the source (6) and drain (8) regions defines a gate region (12). An insulating layer (14, 15) is formed on the substrate (4) and source and drain regions (8), and a cantilever gate structure is formed using a sacrificial layer (60), such that a gate electrode (26) is supported on a cantilever support (28) and a cavity (22) separates the gate electrode (26) from the gate region (12). A conductive layer (34) is formed overlying the gate electrode (26) to provide a heater for the gate electrode (26). The chemical species collect in the cavity (22) and react with the surface (27) of the gate electrode (26).
REFERENCES:
patent: 4020830 (1977-05-01), Johnson et al.
patent: 4411741 (1983-10-01), Janata
patent: 5004700 (1991-04-01), Webb et al.
patent: 5035791 (1991-07-01), Battlotti et al.
patent: 5350701 (1994-09-01), Jaffrezic-Renault et al.
patent: 5417821 (1995-05-01), Pyke
patent: 5576563 (1996-11-01), Chung
Chung Young Sir
Evans Keenan L.
Gutteridge Ronald J.
Hughes Henry G.
Hightower Robert F.
Motorola Inc.
Trinh Michael
LandOfFree
Method for forming a semiconductor sensor FET device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a semiconductor sensor FET device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a semiconductor sensor FET device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-800749