Boots – shoes – and leggings
Patent
1991-11-27
1994-06-07
Dixon, Joseph L.
Boots, shoes, and leggings
364DIG1, 3642466, G06F 1214
Patent
active
053197658
ABSTRACT:
A semiconductor memory unit in which a security code from a security code generation section and an address signal sent from a terminal to the address bus for pseudo access are collated with each other. A control bus changeover circuit connects a control bus to a memory to enable access to the memory when the security code and the address signal coincide with each other. A plurality of memory blocks, each having this security function, are connected in parallel with each other so that the memory blocks have respective independent security functions. A memory block selector selectively provides pseudo access to each of these memory blocks in accordance with an upper address of the address bus. Each memory block is provided with a pseudo access inhibition circuit to inhibit pseudo accessing after the number of pseudo accessing attempts equals a predetermined number.
REFERENCES:
patent: 3806882 (1974-04-01), Clarke
patent: 4590552 (1986-05-01), Guttag et al.
patent: 4713753 (1987-12-01), Boebert et al.
patent: 4797853 (1989-01-01), Savage et al.
patent: 5056009 (1991-10-01), Mizuta
patent: 5142676 (1992-08-01), Fried et al.
van der Meulen et al, "Memory Access To A Chip Card", IBM Technical Disclosure Bulletin, vol. 24, No. 7B, Dec. 1981, pp. 3883-3884.
Dixon Joseph L.
Kim Matthew M.
Mitsubishi Denki & Kabushiki Kaisha
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