Processor with a plurality of microprogrammed units, with antici

Details Processor with a plurality of microprogrammed units, with antici Processor with a plurality of microprogrammed units, with antici

1990-11-30

1994-03-29

Lall, Parshotam S.

395500, 395775, 395800, 395DIG1, 395DIG2, G06F 930, G06F 922

Patent

active

052993183

ABSTRACT:
A data processing system having processors with large instruction sets optimized for the execution of brief instructions. The processor (CPU) comprises a plurality of microprogrammed execution units (EAD, BDP, FPP) communicating with one another and with a memory (MU) by way of a cache memory (CA). One of the units is an addressing unit (EAD). A second unit is a binary and a decimal calculation unit (BDP). A third unit is a floating point calculation unit (FPP) to permit the units to function autonomously, each unit includes its own command block and synchronizing means, for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit.
Each command block includes means for commanding instructions for triggering the execution of the microprogram of the first instruction in standby. The last microinstruction includes an end-of-microprogram indicator, and for certain units an anticipation indication, to condition the command means so as to authorize the execution of the microprogram of the instruction in standby before a preceding instruction has been fully completed.

REFERENCES:
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patent: 4539635 (1985-09-01), Boddie et al.
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patent: 4670835 (1987-06-01), Kelly et al.
patent: 4773035 (1988-09-01), Lee et al.
patent: 5125092 (1992-06-01), Prener
IEEE Transactions on Computers, vol. c-27, No. 3, Mar. 1978 pp. 270-275, L. C. Higbie.
IEEE Transactions on Computers, vol. C 22, No. 2, Feb. 1973, pp. 149-153.

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