Split array binary multiplication

Boots – shoes – and leggings

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G06F 752

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049107011

ABSTRACT:
A system for binary multiplication based upon the modified Booth algorithm incorporating a Booth multiplex decoder, partial modified Booth arrays and partial product reduction adders. The system is comprised of Booth multiplexer cells, Booth multiplexer and adder cells, sign extension cells, and full adder cells interconnected such that the total adder delay through the system is n/4+1 adder delays where n is the number of bits in the multiplier.

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Waser, S. and Peterson, A.; "Real-time Processing Gains Ground with Fast Digital Multiplier"; Electronics; vol. 50, No. 20; Sep. 29, 1977; pp. 93-99.
Thomas C. Bartee, "Digital Computer Fundamentals", Sixth Edition, McGraw Hill, New York, pp. 197-198, (1985).
"Introduction to Arithmetic for Digital Systems Designers" authored by Shlomo Waser, published by CBS College Publishing, Holt, Rinehart and Winston, 1982, see Chap. 4, p. 131, et seq.
Monolithic Memories' Systems Design Handbook, Second Edition, published in 1984, pp. 8-41 to 8-44.
1984 IEEE International Solid-State Circuits Conference publication at pp. 92-93, of the paper presented by Jun Iwamura et al., entitled "A CMOS/SOS Multiplier".

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