Subscriber line interface circuit

Details Subscriber line interface circuit Subscriber line interface circuit

1981-07-21

1984-09-18

Robinson, G. Z.

179170D, H04B 158

Patent

active

044726082

ABSTRACT:
A subscriber line interface circuit for coupling a balanced communication line with unbalanced bidirectional or a pair of unidirectional communication lines. Line current is fed to the line via a low resistance path for maximum current supply, via a circuit which matches the line impedance, and also provides high resistance protection to the output of amplifiers feeding the balanced line. Since a low resistance d.c. current feed is used, a voltage boost is not required. However lightning protection is obtained for the outputs of the amplifiers which feed the line, at the same time as virtually optimum line impedance matching and sufficient line current feed. The circuit is comprised of a balanced line including a lead pair, a pair of matched feed resistors for providing a low resistance path, each connected to one of the pair for applying a d.c. line current from a power source to the line, the total resistance of the feed resistors being a fraction of the d.c. line impedance. A circuit is provided for receiving a signal from the balanced line, and a further circuit applies a predetermined amplitude of the signal received from the balanced line back to the balanced line with a signal aiding polarity so as to raise the apparent impedance of the line for the signal at the lead pair, while allowing d.c. line current to be fed to the line via the low resistance path.

REFERENCES:
patent: 3824344 (1974-07-01), James et al.
patent: 3970805 (1976-07-01), Thomas
patent: 4041252 (1977-08-01), Cowden
patent: 4053722 (1977-10-01), Nahay
patent: 4388500 (1983-06-01), Regan
J. Sergo, Jr.; "DSS Quad Line Circuit"; International Symposium on Subscriber Loops and Services Conference Record; Mar. 1978; pp. 182-184.

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